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74AC374 * 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1988 Revised March 2005
74AC374 * 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
s ICC and IOZ reduced by 50% s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s See 273 for reset version s See 377 for clock enable version s See 373 for transparent latch version s See 574 for broadside pinout version s See 564 for broadside pinout version with inverted outputs s ACT374 has TTL-compatible inputs
Ordering Code:
Order Number 74AC374SC 74AC374SCX_NL (Note 1) 74AC374SJ 74AC374MTC 74AC374PC 74ACT374SC 74ACT374SJ 74ACT374MSA 74ACT374MTC 74ACT374MTCX_NL (Note 1) 74ACT374PC Package Number M20B M20B M20D MTC20 N20A M20B M20D MSA20 MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009959
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74AC374 * 74ACT374
Connection Diagram Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description
Truth Table
Inputs Outputs OE L L H On H L Z
Logic Symbols
Dn H L X
CP

X
IEEE/IEC
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC374 * 74ACT374
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r 50 mA r 50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) (PDIP)
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOZ Maximum Input Leakage Current Maximum 3-STATE Current 5.5 IOLD IOHD Minimum Dynamic Output Current (Note 4) 5.5 5.5 5.5 4.0 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1 V V
IOH IOH IOH IOUT VIN
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND VIL, VIH VCC, GND VCC, GND 1.65V Max 3.85V Min VCC or GND
0.44 0.44 0.44 V
IOL IOL IOL VI VI VO
r0.1 r0.25
r1.0 r2.5
75
PA PA
mA mA
VI (OE)
VOLD VOHD VIN
75
40.0
ICC (Note 5) Maximum Quiescent Supply Current
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC374 * 74ACT374
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current
Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 4.49 5.49
25qC
2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V IOH IOUT VIN
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V
50 PA
VIL or VIH
24 mA
50 PA VIL or VIH 24 mA 24 mA (Note 6) VCC, GND VIL, VIH VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC
IOH 24 mA (Note 6) V
0.001 0.001
0.1 0.1 0.36 0.36
V
IOL IOL VI VI VO VI
5.5 5.5 5.5 5.5 5.5 5.5 0.6
r0.1 r0.25
r1.0 r2.5
1.5 75
PA PA
mA mA mA
VOLD VOHD VIN or GND
75
4.0 40.0
PA
AC Electrical Characteristics
VCC Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 60 100 3.0 2.5 2.5 2.0 3.0 2.0 2.5 2.0 3.0 2.0 2.0 1.5
25qC
50 pF Typ 110 155 11.0 8.0 10.0 7.0 9.5 7.0 9.0 6.5 10.5 8.0 8.0 6.5 13.5 9.5 12.5 9.0 11.5 8.5 11.5 8.5 12.5 11.0 11.5 8.5 Max
TA
40qC to 85q
CCL 50 pF Max MHz 15.5 10.5 14.0 10.0 13.0 9.5 13.0 9.5 14.5 12.5 12.5 10.0 ns ns ns ns ns ns Units
Min 60 100 1.5 1.5 2.0 1.5 1.5 1.0 1.5 1.0 2.0 2.0 1.0 1.0
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74AC374 * 74ACT374
AC Operating Requirements
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW
Note 9: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 2.0 1.0
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
(V) (Note 9) 3.3 5.0 3.3 5.0 3.3 5.0
Guaranteed Minimum 5.5 4.0 1.0 1.5 5.5 4.0 6.0 4.5 1.0 1.5 6.0 4.5 ns ns ns
1.0
0 4.0 2.5
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 10) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 2.0 1.5 1.5 1.5 8.0 8.0 8.5 7.0 9.5 9.0 11.5 8.5 1.5 1.5 1.0 1.0 10.5 10.5 12.5 10.0 ns ns ns ns 5.0 2.0 8.0 9.5 1.5 11.0 ns 5.0 2.0 8.5 10.0 2.0 11.5 ns 5.0 Min 100 TA CL
25qC
50 pF Typ 160 Max
TA
40qC to 85qC
CL 50 pF Max MHz Units
Min 90
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
AC Operating Requirements
VCC Symbol Parameter (V) (Note 11) tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 1.0 0 2.5
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 5.5 1.5 5.0 5.5 1.5 5.0 ns ns ns
5.0 5.0 5.0
Capacitance
Symbol CIN Parameter Input Capacitance Typ 4.5 Units pF VCC OPEN Conditions
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74AC374 * 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC374 * 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74AC374 * 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
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74AC374 * 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74AC374 * 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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